Design of Reliable and Self - Repairing SRAM in Nano - scale Technologies using Leakage and Delay Monitoring *
نویسندگان
چکیده
— The inter-die and intra-die variation in process parameters (in particular, threshold voltage (Vt)) result in large number of failures in an SRAM array degrading the design yield. The adaptive repairing techniques, such as adaptive body bias, can be used to improve the design yield. However, to apply adaptive repairing techniques it is necessary to distinguish between the dies from low-Vt process corners and those from the high-Vt corners. In this paper, we propose an online and low-cost technique to effectively separate dies with different inter-die Vt from each other. The proposed technique is based on online monitoring of leakage or delay and it successfully functions even under high random intra-die Vt variation. Using the online leakage (or delay) monitoring and adaptive body bias, we propose the design of a reliable and self-repairable SRAM to reduce the number of parametric failures. The proposed self-repairable SRAM improves the design yield by 5%-40%.
منابع مشابه
Design and Analysis of 5-T SRAM Cell in 32nm CMOS and CNTFET Technologies
MOS transistor play a vital role in today VLSI technology. In CMOS based design, symmetry should be followed in circuit operation. Most of the complex circuits are allowed to design in CMOS, however, there are several drawbacks present in this complementary based design. CMOS has lost its credentiality during scaling beyond 32nm. Scaling down causes severe short channel effects which are diffic...
متن کامل12th Int'l Symposium on Quality Electronic Design
Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Te...
متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613
As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for i...
متن کاملCharacterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ
One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, f...
متن کاملLeakage Current And Dynamic Power Analysis Of Finfet Based 7t Sram At 45nm Technology
As technology is scaled down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 45nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs eff...
متن کامل